Parity checking is a well known method for detecting errors in transmitting data. In accordance with such method, a parity bit is or is not added to a packet, e.g. a byte, of binary digits so as to maintain the total number of bits, including the parity bit, as an odd or an even sum. When the packet is transmitted, the total number of bits is counted and if the sum is not odd or even as it is supposed to be, a parity error has occurred. Current high performance personal computers have thirty two bit wide memory data paths in which data is arranged in four eight bit bytes each byte being associated with one parity bit. A parity checking circuit is connected to a data path and upon detecting a parity error, it sends a signal that latches up a flip flop which generates a parity check signal. The parity check signal in turn causes a hardware interrupt to be sent to a processor and a software interrupt handling routine analyzes the error, displays an error code on a display, and halts operation of the computer.
To improve system performance, the memory may be arranged as a sixty four bit banked memory wherein data is stored in memory in odd/even double words of thirty two bits each. On each memory access, parity is read and checked sixty four bits at a time and an error cannot be isolated to a particular memory bank, module, or field replaceable module. It is desirable to be able to isolate the error to the bank from which the error arose.
The prior art of which we are aware recognizes the problem but provides solutions that are more complicated and more costly than the solution provided by our invention. In the prior art, a parity check circuit is associated with each bank of memory along with some additional hardware that is also associated with each bank. Examples of such prior art are the following. IBM Technical Disclosure bulletin Vol. 20, No. 11B, April 1978, pages 4839 and 4834 disclose "Microcode Integrity Checking" in which a plurality of modules respectively feed parity check circuits and counters. The modules store count fields, in addition to the data and parity bits. Single bit errors are detected by the parity check and double bit errors are detected by the counters. The article suggests it is "easy to determine which module has failed" but fails to describe precisely how it is done.
JP 56-19593 briefly describes a "Parity Check Processing System for Memory" in which two parity check circuits from two memory banks feed a status display register. The result from the check circuits is "respectively reported separately on the status display register", and a processor can then take some action based on the content of the register. The details of the separate reporting are not disclosed.
U.S. Pat. No. 4,809,276 - R. A. LEMAY et al discloses a "Memory Failure Detection Apparatus" having banks of memory and error detection and correction circuits associated with each bank. A counter is also associated with each bank and records the number of corrections that have occurred. A processor periodically polls the counters and provides messages to replace memory boards.